Date: Wednesday, 25 April, 2012
Time: 9.05am - 5.00pm
Venue: Tech West
Brought to you by SEMI Singapore - Advanced Packaging Technologies Committee
Moring Session Chair:
Afternoon Session Chair:
Moore’s law has reliably driven Silicon scaling for several decades. As the semiconductor manufacturing world moves into the “More than Moore” 2.5D/3D space, a wealth of opportunities are becoming available that further increase the functionality and performance of semiconductor ICs. For example, silicon circuit designers increasingly find that by designing a Silicon system in 2.5D/3D, they are not limited to using one Silicon technology node (e.g., 40nm or 28nm CMOS) or a single technology (e.g Logic, DRAM, Flash, MEMS). Enabled by 2.5D and 3D IC technology, designers can now design and build high-performance and energy-efficient systems using heterogeneous technologies such as CMOS (including multiple logic, memory technology nodes), MEMS, Si Photonics, etc.
While technology opportunities abound, moving to 2.5D/3D manufacturing poses significant challenges to designing, fabricating, assembling and testing of 2.5D/3D ICs in a seamless manner. Manufacturing heterogeneous technologies for 2.5D/3D ICs calls for both industry and R&D organizations to address the challenges. This calls for a learning curve across design-houses, fabs/foundries, assembly/test providers, EDA developers, and research-institutes. Among other things, the learning curve calls for a re-adjustment of roles and responsibilities in the manufacturing flow. A collaborative approach is essential for the industry to harness 2.5D/3D IC technologies successfully. An eco-system that is optimized for manufacturing 2.5D/3D ICs holds the key to transferring 2.5D/3D technologies into high-volume manufacturing.
09:05 – 09:15
09:15 – 09:50
* Keynote: Embracing the Era of 2.5D & 3D Ics
10:15 – 10:40
10:40 – 10:50
10:50 – 11:15
11:15 – 11:40
11:40 – 12:05
12:05 – 12:30
Via Reveal Technology for 3D-IC Manufacturing
12:30 – 13:30
13:25 – 14:00
* Keynote: 2.5-D ICs: Just a Stepping Stone or a Long Term Alternative to 3-D?
14:00 – 14:25
14:25 – 14:50
14:50 – 15:15
15:15 – 15:25
15:25 – 15:50
15:50 – 16:10
TSV and Interconnects for 2.5D and 3D Integration
Mr. Sesh Ramaswami, Managing Director Strategy, Applied Materials
16:10 – 17:00
Panel Discussion Topic:
2.5D and 3D: On the Way to HVM
|Dr. Ho Ming Tong, General Manager & Chief R&D Officer, ASE Group |
Dr. Ho-Ming Tong is presently Chief R&D Officer & General Manager of Group R&D, ASE Group and Advisory Committee Member of National Chip Implementation Center, National Applied Research Laboratories, Republic of China (Taiwan). Prior to joining the ASE Group, Dr. Tong served 13.5 years at IBM as Research Staff Member at Thomas J. Watson Research Center , and as Senior Engineering Manager at IBM’s East Fishkill Facility responsible for leading-edge IC and package development covering C4 plating and the plated copper wiring IC technology.
Dr. Tong was elected IEEE Fellow for leadership in leading-edge integrated circuits technology and also Fellow of the Chinese Society for Management of Technology. Among the awards Dr. Tong received were (1) the Electronics Manufacturing Technology Award from IEEE Components, Packaging and Manufacturing Technology (CPMT) Society, (2) the John A. Wagnon Technical Achievements Award from The International Microelectronics And Packaging Society, (3) IBM Watson Research Division Award, (4) IBM Master Inventor, (5) the R&D Management Innovation Award from the Ministry of Economic Affairs, Republic of China, (6) the Outstanding Research Award of Pan Wen Yuan Foundation and (7) seven IBM invention plateau awards. Dr. Tong received his Ph.D. degree from Columbia University in chemical engineering. He has authored/co-authored 112 patents, 100+ technical publications, as well as 2 books and 2 special journal issues on electronic packaging.
Derek Hinkle is the Sr. Director of Advanced Packaging at Aptina Imaging. In his current role he is responsible for package R&D, New Product Introduction and supply chain development.
He has 24 years of industry experience in various technical and operational positions and prior to Aptina he worked at Micron Technology. At Micron he was focused on packaging for Memory and CMOS Image Sensor products and served as Assembly Engineering Manager before joining Aptina as a Director of Operations.
He led the outsourcing effort during the spinout of Aptina from Micron Technology. The scope of which included transitioning the supply chain from a captive manufacturing model to an OSAT model. As an extension of this effort he is continuously evaluating supply chain opportunities to understand how to best meet the ever growing complexity of CIS packaging solutions.
Camelia Rusu is an Engineering Director leading the 3DIC group in Lam Research Corporation. She received her PhD in Physical Chemistry-Surface Science from University of Pittsburgh, Pennsylvania, USA.
Dr. Klaus Hummler is Senior Principal Engineer and Program Manager of the 3D Integration, Test Vehicles, and Reliability Program in SEMATECH’s Interconnect Division, which focuses on new interconnect technologies for tomorrow’s advanced computer chips.
|Dr. Itsuo Watanabe, Executive Officer & General Manager of Tsukuba Research, Hitachi Chemical |
Dr. Itsuo Watanabe is currently an Executive Officer and a General Manager of Tsukuba Research Laboratory of Hitachi Chemical Co., Ltd.. He joined Hitachi Chemical Co., Ltd. in 1982 and had conducted research and development on high performance polymeric materials for more than 20 years.
He received his MS degree in chemistry from Utsunomiya University and his PhD degree in polymer science from Kyoto University.
He serves as a member of the technical committee of the international conferences such as international conference on “Electronics Packaging”. He served as a general chairman of 2005 ICEP. He has presented a number of invited papers at international conferences in the area of semiconductor packaging technologies.
He received the Award of the Society of Polymer Science, Japan for the research and development of anisotropic conductive films in 2003.
He also received John A. Wagnon Technical Achievement Award of International Microelectronics and Packaging Society for outstanding technical contributions to microelectronics technology in 2005.
|Dr. Steven T. Mayer, Director and Principal Engineer New Products Development Group, Novellus Systems |
- Bachelor’s degree University of New York, Buffalo, Chemical Eng.
- Ph.D., University of California, Berkeley, Electrochemical Eng.
Electrochemical interfaces using linear and non-linear spectroscopy.
‘89: Lawrence Livermore National Defense Laboratories: Strategic Defense Initiative (SDI): Interceptor Computing and Power Division
- Pioneering work in copper damascene integrated circuits processing, lithium-ion batteries for space, and carbon-aerogel supercapacitors.
1993: Co-Found Polystor Corp, President, New Product Engineering:
First US lithium-ion battery manufacturing company
1995: Founded PowerStor Supercapacitors, CTO. Left when company was acquired by Copper Bussmann in 1998.
1998: Novellus Systems- Fellow
Technology Leader: SabreTM copper-damascene development group.
Has held various position in the New Products Development Group Currently supporting the rapidly growing 3D Packaging, Microbump and TSV interconnect “revolution”.
Steve is the inventor of 90+ issued US patents.
Bob Patti attended Rose-Hulman Institute of Technology, earning Bachelor of Science degrees in both physics and electrical engineering. He founded an R&D company specializing in high-performance systems and ASICs and participated in the design of over 100 chips in the course of 12 years. Tezzaron Semiconductor grew from that company to become a leading force in 3D-IC technology, building its first working 3D-ICs in 2004. Today Bob is the CTO of Tezzaron, using wafer-level stacking processes to create ultra high-density 3D memory products and other semiconductor sub-components. He received the SEMI Award for North America in 2009, served as Vice-Chairman of JEDEC's DDRIII / Future Memories Task Group, and holds 16 US patents, numerous foreign patents, and many more pending patent applications in deep sub-micron semiconductor chip technologies.
|Dr. Tee Tong Yan, Vice President of Engineering, Silecs International |
Dr. Tee Tong Yan currently is the Vice President of Engineering in Silecs International, an advanced electronic material supplier. Dr. Tee has more than 15 years of working experience in advanced packaging and material R & D management, capability development and strategic planning. Prior to joining Silecs, he holds senior R&D positions in Nepes, Amkor and STMicroelectronics. He has over 150 publications in journals, conferences and book chapters. He holds Bachelor, Master and PhD Degrees in Mechanical Engineering.
David Butler currently serves as the Vice President Marketing at SPTS Technologies. With 22 years of experience in the semiconductor capital equipment and related industries, he first joined Electrotech in 1988 as a Senior Process Engineer, and subsequently moved into a product marketing role, managing PVD products. In 2004, he assumed the position of Director of Marketing for the PVD/Etch/CVD products at Trikon Technologies. Following the merger of Trikon and Aviza in 2006, he was appointed Vice President of Marketing for Aviza Technology.
In 2009, Mr. Butler was promoted to Vice President of product and corporate marketing with the formation of SPTS. In this position, he currently oversees all global marketing activities for SPTS’ full range of PVD, Etch, CVD and thermal products.
Mr. Butler graduated from Loughborough University with a B.S. in Physics. He has published numerous technical articles and delivered multiple presentations on wafer processing technologies worldwide.
E. Jan Vardaman is president and founder of TechSearch International, Inc., which has provided analysis on technology and market trends in semiconductor packaging since 1987. She is co-author of How to Make IC Packages (published in Japanese by Nikkan Kogyo Shinbunsha), a columnist with Circuits Assembly Magazine, and the author of numerous publications on emerging trends in semiconductor packaging and assembly. She served on the NSF-sponsored World Technology Evaluation Center study team involved in investigating electronics manufacturing in Asia and on the U.S. mission to study manufacturing in China. She is a member of IEEE CPMT, IMAPS, IPC, MEPTEC, and SEMI. She received the “Die Products Industry Achievement Award,” at the 14th Annual International KGD Packaging and Test Workshop in September 2007. She was elected to two terms on the IEEE CPMT Board of Governors. Before founding TechSearch International, she served on the corporate staff of Microelectronics and Computer Technology Corporation (MCC), the electronics industry’s first pre-competitive research consortium.
Dr. Raj Pendse is Vice President and Chief Marketing Officer at STATS ChipPAC where he is responsible for marketing and business development of the Company’s Advanced Technology products. Raj has been with STATS ChipPAC for over 12 years in various leadership positions including product engineering, technology and marketing. Prior to joining STATS ChipPAC, Raj held various positions in package engineering and R&D at National Semiconductor Corp and Hewlett-Packard Labs. His work has spanned the gamut from packaging of high-end microprocessors, ASIC and graphics products to low-cost packaging solutions for logic and analog devices that find use in mobile phones and consumer products. His most recent focus has been on Flip Chip and 3D Wafer Level Packaging. Raj completed his BS in Materials Science from IIT Bombay with Top in Class honors and his Doctorate in Materials Science from UC Berkeley.
|Mr. Vincent Tong, Senior Vice President, Xilinx Inc |
Vincent Tong serves as senior vice president of worldwide quality and new product introductions, and executive leader for the company’s Asia Pacific region. As executive leader for Xilinx Asia Pacific, Tong’s charter is to expand the company’s presence and accelerate business development in a region that is experiencing phenomenal growth, and is in turn a critical source of Xilinx current and future growth.
In his role as Xilinx senior vice president, Tong is responsible for all aspects of quality assurance across Xilinx programmable solutions. His worldwide quality organization is chartered with driving continuous improvement of the company's corporate quality methodology for design, manufacture, training, measurement, and post-sale customer support for Xilinx products, and for reliability engineering of all product manufacturing technologies.
Tong also leads a global team to direct all new product introductions to achieve fastest time-to-market at the highest level of quality. Tong oversees the engineering teams responsible for test, package, assembly development, yield improvement and product engineering, in support of all new product introductions and mature products in production.
In addition, Tong manages advanced technology partnerships, overseeing all quality control and qualification programs and directing all continuous improvement initiatives with wafer foundries, subcontractors and other key technology suppliers (e.g., substrate suppliers, assembly, DFT and DFM vendors, ATE and semiconductor manufacturing equipment manufacturers).
Tong joined Xilinx in 1990 after serving in a variety of development, design, fabrication technology, product and test engineering positions at Monolithic Memories and Advanced Micro Devices.
Tong holds a B.S. in engineering and computer science from the University of California, Berkeley, and completed the executive development program at Stanford Business School. He holds seven U.S. patents.
Sesh Ramaswami is Managing Director, Strategy in the Silicon Systems Group at Applied Materials. In this capacity, his responsibilities include program definition and execution, defining and driving external collaboration and co-leading internal process integration programs for Through-Silicon-Via (TSV) within the wider context of wafer level processing for advanced packaging. He is a co-author and contributor of a book recently published by McGraw Hill, entitled 3D IC Stacking Technology.
Since its first adoption in cell phones a decade ago CMOS Image Sensor (CIS) solutions have taken over CCD to become the dominant image acquisition device in use today. CIS solutions are now so ubiquitous that they are embedded in our everyday life and the adoption rate for current and new applications continues to grow. Based on iSuppli’s forecast, the CIS market will grow at a compounded rate of 15% a year over the next 3 years.
The requirement for increased performance and miniaturization has posed unique challenges and is one of the key reasons for CIS companies to be among the first adopters of 3D technology. Future imaging solutions will post ever increasing demands on performance and functionality while driving decreasing requirements on size, power and cost.
This paper will provide an introduction of CIS, expanding applications and technology trends. It will also discuss the drivers, requirements and challenges of addressing those needs via 3D IC technologies and the associated supply chain implications.
Implementation of TSV modules in production for 3DIC applications has become a technical and fundamental reality to contend with. Almost every semiconductor manufacturer is either directly working on TSV module design and development, or – if fabless, is working with partners for implementation of TSV modules. This talk will primarily focus on the etch requirements for the TSV module. Etch challenges can vary widely with different applications, such as CIS, interposer or real 3DIC. Recent development and upgrades have been made to address these market requirements, whether for silicon or glass substrates. We will show results of an etch system capable to etch multi-film stacks in addition to the deep silicon required to form TSVs. Substrates are patterned with either photoresist or dielectric hard mask, ranging from the submicron-level to several tens of microns, with aspect ratios varying from small to >20.
Dr. Itsuo Watanabe, Executive Officer & General Manager of Tsukuba Research, Hitachi Chemical
3D semiconductor packeging technologies such as wire bonding die-satcked Chip Size Package(CSP), Package on Packege(POP) and Through Silcon Via(TSV) technology have been of much interest because they provide the highest packaging density and electrical performance among conventional semiconductor packaging technologies. 3D semiconductor packaging technology is the key technologies to realize a highly integration of logic and memory devices. Therefore, recently the 3 D semiconductor packaging technologies have been widely used in varios devices such as image sensor. logic and maemory devices. The high parfoemance matrials such as RDL materials, underfill, die bonding films, subtrate materials are very issential in improving the 3D semiconductor packaging technologies. In this talk, materials trends and challenges for 3D semiconductor packaging tecdhnologies are discussed.
Dr. Klaus Hummler, Senior Principal Engineer and Program Manager of 3D Interconnect Division, SEMATECH
For 2.5D and 3D integration to reach its full potential, the chip-to-interposer and chip-to-chip interfaces must support a very large number of power and signal connections. The current, mostly solder-based interconnect schemes will not scale sufficiently due to mechanical, electrical, thermal, and reliability limitations. SEMATECH’s interconnect division has identified Cu-Cu direct bonding (CuDB) as a promising technology to aggressively scale chip-to-chip interconnects, so that the interconnect scheme will keep pace with through-silicon-via (TSV) and on-chip interconnect scaling. Recent progress and remaining technical and economical hurdles in realizing high volume manufacturing of CuDB interconnects will be discussed.
Mr. Andrew Pindar, Business Development Manager, Novellus Systems
Along with the adoption of modern semiconductor front end processes such as electroplating for the packaging world, there is an opportunity to update other processing applications including conventional resist strips and cleans.
Traditionally a low priority and handled mostly by wet processing, the high costs of some chemicals used for resist strip in the packaging environment can permit dry processing alternatives to be considered, both on the basis of costs and also technical performance.
In addition, current generation high throughput tools provide more economic alternatives for descum and clean functions. This paper will provide examples of several applications showing typical performance achievable and also a rough comparison of costs.
Mr. Robert Patti, CTO and VP of Design Engineering, Tezzaron Corporation
Next generation semiconductors are facing extreme lithography and processing challenges. Another approach to the continuous push of geometric shrinking is the use 3D circuit integration. 3D integrated circuits blur the line between what is semiconductor processing and what is packaging. The use of fine feature vertical interconnect allows a virtually seamless extension of 2D circuits into 3D that provides not only better circuit designs but also best of class semiconductor optimization with potential cost reduction and improved yield. The speaker will discuss the benefits and new possibilities that 3D-ICs will provide. A discussion and examples of current developments and future 3D circuits will also be given.
Dr. Steven T. Mayer, Director and Principal Engineer New Products Development Group, Novellus Systems
Electroplating has been used in the electronics packaging industry since the advent of integrated circuit manufacturing. Process-displacement growth during this time was primarily in a few relatively small but technically opportunistic specialty markets (e.g. C4 flip chip packaging). Now, the rapidly-expanding performance demands from the gambit of electronics market segments is driving an exploding need for higher I/O, shrinking form factors and reduced power consumption. Increasingly, conventional mechanical and serial packaging technologies are unable to meet these emerging performance requirements irrespective of cost. This is the underlying force behind the broad-based industry drive for advanced 2.5D/3D packaging, and the adoption of electrometallization.
In the area of BEOL interconnects, copper damascene electrodeposition is a proven process that enables cost effective metallization of extremely fine pitch structures, and many of the same strengths which have solidified plating as the BEOL metallization process of choice extend to copper/lead-free micropillars, microbumps and through silicon vias (TSV’s). However, successful achievement of the cost, uniformity, morphology, composition, and stability goals requires overcoming fundamental challenges in managing transport, chemical, kinetic and thermodynamic driving forces behind each process. In this presentation, I discuss these challenges and offer some solutions and general approaches to overcoming them.
While 3-D IC technology offers significant benefits, it also presents new design and manufacturing challenges. A simpler approach known as “2.5-D” offers many of the benefits of full 3-D, but without some of the drawbacks. In this talk, Xilinx Senior Vice President Vincent Tong will discuss the progression of 3-D IC technology and technical challenges for 3-D vs. 2.5-D, present a 2.5-D case study, and provide a glimpse into future directions for the industry in its quest to achieve “more than Moore” with each new manufacturing process node.
Dr. Tee Tong Yan, Vice President of Engineering, Silecs International
Silecs is a technological leader in developing and producing advanced polymers materials, and an innovator of Siloxane materials used in the microelectronics industry, particularly for digital imaging, semiconductor packaging, solar cell and flat panel display manufacturing. This presentation will share the current development of novel materials for applications in 3D and advanced packaging.
Dr. Raj Pendse, Vice President and Chief Marketing Officer, STATS ChipPAC
While the application space for 2.5D and 3D integration has grown rapidly over the past 1-2 years, the development of an ecosystem to design and manufacture real products has been notably sluggish. In this paper, we first review recent developments in the architecture, design, process technology and manufacturing infrastructure for 2.5D and 3D TSV products in the industry as a whole and the OSAT industry in particular. We map the future technology development trends at the OSAT’s, the evolving biz models and how that will contribute to the overall 2.5D/3D manufacturing infrastructure. We also look holistically at alternative emerging approaches to integration such as thin film wafer-level packaging, their respective sweet spots within the broader application space and how they would shape to the overall ecosystem. We close with a projection of the future direction and outlook for product introductions in the Mobile and Computing areas.
Miss. Jan Vardaman, President, TechSearch International
As 2.5D and 3D packaging move into the commercialization phase, there are some remaining technical and business issues to resolve. Key process steps still requirement improvement and higher yield. New materials are needed. Once the technical issues are resolved, business issues such as supply chain handoff remain. As the boundry between the foundry process and the assembly process continue to blur, there is a struggle to determine which organizations can best meet customer needs in assembly and test. This presentation outlines the strengths of both and examines supply chain implications in the division of labor and industry readiness.
Mr. David Butler, Vice President of Marketing, SPTS
In 3D-IC manufacturing, after the through silicon vias (TSV’s) have been formed in the device wafer or interposer, the substrate must be readied for connection to the outside world. The first module in this sequence is the “via reveal” step.
The full thickness TSV’d wafer is temporarily bonded, device side down, onto a carrier typically made from glass or Si. The backside of the wafer is ground to a point approximately 10 to 15 microns above the tips of the Cu filled TSV’s. The substrate is then put into a Si etch module, and the remaining Si is dry etched until the tips of the TSV’s are exposed, the “via reveal” step. PECVD nitride and/or oxide is then deposited over the TSV tips, with a final CMP step to planarise the surface prior to re-distribution metallization.
This presentation will focus on the Si etch and PECVD parts of the via reveal module. Challenges will be discussed including minimizing total thickness variation (TTV), endpointing the via reveal step, and depositing low leakage dielectrics at temperatures suitable for temporarily bonded substrates. The slides will also discuss how temporary bonding glues can disrupt plasma based processes, and how those disruptions can be avoided.